Providing design flexibility in a cache by allowing a variety of size and associativity choices, while maintaining the speed of the cache in locating/storing a requested element, may be highly advantageous for architectures that utilize a cache. Traditionally, there have been three types of cache organizations that have been used: the fully associative, the k-way set associative; and the direct mapped cache organizations.
In a fully associative cache organization, each item of information from a main system memory is stored as a unique cache entry. There is usually no relationship between the location of the information in the cache and its original location in main system memory.
Typically, a set associative cache divides the cache memory into k banks of memory, which is also known as k ways. Usually, a set associative cache logically views memory as broken up into pages. Every location within a page of memory is capable of being stored in one location of each of the k ways, which forms a set of locations capable of storing multiple memory locations. When a memory request is made, the set associative cache will typically compare the memory request with a cache location in a number of the ways.
However, as power savings, and heat dissipation due to power consumption, become more prevalent concerns, power consumption of individual parts of processors, such as caches, becomes an ever pressing concern. In fact, current caches make up a good percentage of active power dissipated. This level of power consumption is usually due to speculatively reading multiple ways of a given set to avoid the performance loss associated with waiting for a tag array to denote a single way to be accessed. Therefore, as caches grow both in size and the number of ways, more power is consumed reading multiple locations to provide in response to determining a way to be loaded from.